note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated.com/errata . MAXQ1850 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated? website at www.maximintegrated.com. evaluation kit available deepcover secure microcontroller with rapid zeroization technology and cryptography abridged data sheet 19-5265; rev 4; 1/13 general description deepcover embedded security solutions cloak sensitivedata under multiple layers of advanced physical security to provide the most secure key storage possible. the deepcover secure microcontroller (MAXQ1850) is a low-power, 32-bit risc device designed for electronic commerce, banking, and data security systems. it com- bines high-performance, single-cycle processing, sophis- ticated tamper-detection technology, and advanced cryptographic hardware to provide industry-leading data security and secret key protection. physical security mechanisms include environmental sensors that detect out of range voltage or temperature conditions, responding with rapid zeroization of critical data. four self-destruct inputs are provided for addition- al tamper response. an internal shield over the silicon provides protection from microprobe attacks. a high- speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. to protect data, the MAXQ1850 integrates several high- speed, analysis-resistant encryption engines. algorithms supported in hardware include aes (128-, 192-, and 256-bit), des, triple des (2-key and 3-key), ecdsa (160-, 192-, and 256-bit keys), dsa, rsa (up to 2048 bits), sha-1, sha-224, and sha-256. the advanced security features of the MAXQ1850 are designed to meet the stringent requirements of regulations such as itsec e3 high, fips 140-2 level 3, and the common criteria certifications. the MAXQ1850 includes 256kb of flash memory and 8kb of secure, battery-backed data sram. several communication protocols are supported with hardware engines, including iso 7816 for smart card applications, usb (slave interface with four end-point buffers), an rs- 232 universal synchronous/asynchronous receiver- transmitter (usart), an spi interface (master or slave mode support), and up to 16 general-purpose i/o pins. other peripherals supported on the MAXQ1850 include a true hardware random-number generator (rng), a real-time clock (rtc), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (pwm) operations. features ? high-performance, low-power, 32-bit maxq30risc core ? single 3.3v supply enables low power/flexibleinterfacing ? dc to 16mhz code execution across entireoperating range ? 65mhz cryptography engine execution to reduceprocessing time ? on-chip 2x/4x clock multiplier ? 33 instructions ? 16-bit instruction word, 32-bit internal data bus ? 16 x 32-bit accumulators ? up to 16 general-purpose i/o pins ? 5v tolerant i/o ? virtually unlimited software stack ? optimized for c-compiler (high-speed/density code) ? memory features ? security features ? additional peripherals ? low-power consumption applications ordering information par emp range pin-package MAXQ1850-bns+ -40 c o +85 c 40 tqfn-ep* MAXQ1850-lns+ -40 c o +85 c 49 csbga MAXQ1850-dns+ -40 c o +85 c bare die + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. selector guide appears at end of data sheet. see the detailed features section for complete list of features. electronic commerceemv banking secure access controlsecure data storage pay-per-playcertificate authentication electronic signature generation deepcover is a trademark of maxim integrated products, inc. emv is a registered trademark of emvco llc. downloaded from: http:///
deepcover secure microcontroller with rapid zeroization technology and cryptography MAXQ1850 12 maxim integrated abridged data sheet note to readers: this document is an abridged version of the full data sheet. to request the full data sheet, go to www.maximintegrated.com/MAXQ1850 and click on request full data sheet . core osc ecdsa rsa 16kb rom 8kb nv sram gpio maxq30 core iso 7816 spi usb usart dsa des aes rng timers jtag/ debug 256kb flash crypto osc rtc pll 32khz 12mhz MAXQ1850 note: the block diagram shows a typical system clock used to support usb operation at 12mhz. multiple external crystal/clock options are available. block diagram detailed features ? high-performance, low-power, 32-bit maxq30risc core ? single 3.3v supply enables low power/flexibleinterfacing ? dc to 16mhz code execution across entireoperating range ? 65mhz cryptography engine execution to reduceprocessing time ? on-chip 2x/4x clock multiplier ? 33 instructions ? three independent data pointers accelerate datamovement with automatic increment/decrement ? 16-bit instruction word, 32-bit internal data bus ? 16 x 32-bit accumulators ? up to 16 general-purpose i/o pins ? 5v tolerant i/o ? virtually unlimited software stack ? optimized for c-compiler (high-speed/density code) ? memory features 256kb flash, composed of 2048 byte sectors (1k erase/write cycles per sector) 8kb battery-backed data sramdedicated cryptographic memory space ? security features unique idtamper detection with rapid key/data destruction four self-destruct inputs hardware aes and des engines public key cryptographic accelerator for dsa, ecdsa, and rsa supports sha-1, sha-224, and sha-256real hardware rng and prng hardware crc-32/16 unalterable, battery-backed real-time clock ? additional peripherals power-fail warningpower-on reset/brownout reset jtag i/f for system programming and accessing on-chip debugger usb i/f with four end-point buffersiso 7816 smart card uart with fifo four 16-bit timer/counters, two with pwm function spi and usart communication portsprogrammable watchdog timer ? low-power consumption 150na typical current draw in battery-backed mode, preserving 8kb nv sram and with security sensors active (460na with rtc active) downloaded from: http:///
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